The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effectively applicable to a logic LSI comprising circuit elements including MISFETs (Metal-Insulator-Semiconductor Field Effect Transistor) and multi-layer wiring structure.
For an ASIC (Application Specific Integrated Circuit or Application Specific Standard Product), there are, for example, gate arrays and standard cell LSIs (called also a cell based IC). The gate array is a typical example of the semiconductor integrated circuit device fabricated by the master slice system. This gate array is prepared by arranging many basic cells uniformly on a semiconductor substrate in advance, and is used to fabricate an LSI with desired logic circuits by connecting the basic cells with signal wirings in accordance with the user's requirements.
The basic cell comprises CMOS (Complementary MOS) or BI-CMOS (Bipolar CMOS) elements, for example.
The feature of the semiconductor integrated circuit device, for which a master slice system of this kind is adopted, is that various logic circuits can be formed simply by varying its wiring patterns, thereby developing many varieties in a short period of time.
In a semiconductor integrated circuit device having a multi-layer wiring structure such as the gate array mentioned above, the power supplied from the outside is transmitted to the inside of the semiconductor integrated circuit device through a pair of supply wirings. One of the pair of supply wirings is connected to an external power source terminal to which a higher level voltage (hereinafter referred to simply as a source voltage V.sub.DD) is supplied while the other is connected to another external power scarce terminal to which a lower level voltage (hereinafter referred to simply as an ground voltage V.sub.ss) is supplied.
On the circumferential part of a semiconductor chip having the above semiconductor integrated circuit device formed thereon, there are arranged in succession bonding pads which provide electrical connections with the outside, and I/O cells which selectively function as an input/output buffer circuit, an output buffer circuit, or an input buffer circuit. In an inner area encircled by the I/O cells on its circumference (cell region), a plurality of basic cells are arranged regularly. On the plural wiring layers on the I/O cells and the cell region, the signal wirings and supply wirings are arranged by an automatic arrangement and wiring system. On the wiring layer of a first layer in the cell region, the supply wirings (supply wirings for cells) are formed along the arrangement of the basic cells to supply each cell with the electric power. Likewise, on the wiring layer of the first layer in the cell region, the signal wirings (wirings in a cell) are formed for connection within basic cells. Also, on the wiring layer of the second layer on the basic cells and further on the upper wiring layers (a third layer, fourth layer, etc.), the signal wirings are formed to connect the basic cells.
In this respect, for an ASIC such as this, there is a disclosure, for example, in ISSCC (International Solid-State Circuits Conference) Digest of Technical Papers, pp.88-89, 270, February 1990, and for a standard cell LSI, there is a disclosure, for example, in the "Design of CMOS VLSIs", pp. 275-279, published by Baifukan Co., Ltd., in 1989.
The present inventors have found the following problem in the course of studies on the micro-miniaturization of a semiconductor integrated circuit device formed by the aforesaid ASIC arrangement and the achievement of a higher operational speed of the system.
With the progress in the micro-miniaturization and higher integration of a gate array, the size of basic cells become smaller, and the wiring density of signal wirings and supply wirings arranged in the cell region becomes higher. Then, for example, in a CMOS gate array having circuit elements with MISFETs comprising basic cells in which the supply wirings for cells and wirings in a basic cell are formed on the wiring layer of a first layer, the arrangement of connecting holes (contact hole) to connect the semiconductor region (diffused layer) serving as source and drain regions of the MISFET and the wirings on the first layer is restricted, making it difficult to secure the contact hole in a wide area. As a result, it becomes impossible to obtain a sufficient area for the semiconductor regions and the wirings of the first layer, thus increasing the diffused layer resistance and contact resistance, i.e., the parasitic resistances of the MISFET. This presents the problem of hindering the achievement of a faster operational speed of the circuits.
Also, in order to reduce the size of basic cells for a higher integration, the width of supply wirings for cells and wirings in a basic cell must be miniaturized. Then the current density of the supply wirings for cells formed on the wiring layer of the first layer becomes high, and due to the influence of electromigration, etc., the electrical reliability of the semiconductor integrated circuit is lowered.
In this respect, there is disclosed, for example, in Japanese Patent Laid-Open No. 70542/1988 of Mar. 30, 1988 a technique of reducing the diffused resistance and contact resistance in a semiconductor integrated circuit device with the wirings in a basic cell and supply wirings for cells formed therein. In this publication, the wirings of the first layer and the semiconductor regions serving as source and drain regions of MISFETs are formed against the gate electrode of the MISFET in a self-alignment manner, and are connected through the contact electrodes provided on the gate electrode and the insulating film. At the same time, the circuit design has been made easier by arranging each of the leader electrodes beforehand almost in the entire area over the respective semiconductor regions serving as source and drain regions.
Also, for a "sea of gates" type CMOS gate array, there is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp.1280-1285, VOL. 24, No. 5, October 1989 a technique for connection within basic cells and within logic circuits (macro-cell) composed of basic cells, and for connection between the logic circuits by the wiring layer of a second layer using the area over the basic cells as a wiring region. According to this article, the second-layer wirings extend in parallel with the rows of basic cells, and substantially the whole area over the basic cells is used as wiring regions to increase the number of wiring channels.
On the other hand, as a technique of reducing the above-mentioned diffused layer resistance and contact resistance, there is known a technique of bonding a thin film made of high melting metal such as W, Mo, etc., or its silicide (WSi.sub.2, MoSi.sub.2, etc.) to the semiconductor regions of MISFETS, i.e., the so-called Saliside technique. However, this technique has a disadvantage that a part of the thin film mentioned above is thrust into the semiconductor region when it is formed thereon, and that there is a tendency to introduce a deep pn junction, thus presenting a problem that its application is not suited for the fabrication process of a highly integrated MISFET which requires an extremely shallow formation of the pn junction (semiconductor region) for the desired miniaturization.
Typically, a semiconductor integrated circuit device using a standard cell system included in the design concept of ASICs is designed and developed in support of an automatic routing system using a computer (DA: Design Automation). The standard cell system is a system such that previously a plurality of types of properly designed macro-cells (functional circuit block) are inputted to a DA, several macro-cells are arranged according to necessity, and these macro-cells are interconnected. Therefore, semiconductor integrated circuit devices using the standard cell system are suitable for small-quantity multi-kind production because the design and development periods are short and the integration degrees and circuit performances are relatively high.
For the semiconductor integrated circuit devices using this type of system, a technique for realizing a high integration degree and high-speed circuit operation was reported in, for example, Section 8.2 "0.8 m 1.4 MTr. CMOS SOG based on Column Macro-cell" CICC (Custom Integrated Circuits Conference) in 1989.
The semiconductor integrated circuit device described in this report has a two-layer wiring structure in which two wirings, i.e., first-layer power supply voltage wiring and first-layer reference-voltage wiring extending in the same first direction spaced from each other and wirings, i.e., second-layer power supply voltage wiring and second-layer reference-voltage wiring extending in the second direction perpendicular to the first direction spaced from each other are arranged. That is, the power supply wirings of the first-layer power supply voltage wiring, first-layer reference-voltage wiring, second-layer power supply voltage wiring, and second-layer reference-voltage wiring are arranged like a grid.
A plurality of basic cells (unit cells) each serving as a basic circuit pattern are repetitively arranged in areas defined and enclosed by the power supply wirings arranged like a grid. Each basic cell comprises a plurality of p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) connected in series and a plurality of n-channel MOSFETs or a plurality of CMOSs (Complementary MOSs) connected in series. The direction of the gate length of a plurality of n-channel MOSFETs is the same as the extending direction (the second direction) of the second-layer power supply voltage wiring and second-layer reference-voltage wiring.
Interconnection of a plurality of the MOSFETs arranged in the basic cells (wiring in basic cell) is made by the first-layer signal wiring. Power is fed to a plurality of the MOSFETs arranged in the basic cells mainly from either of the second-layer power supply voltage wiring and second-layer reference-voltage wiring.
Adjacent basic cells are interconnected with the first-layer signal wiring (in the same wiring layer) integrated with the first-layer signal wiring used for interconnection in the basic cells. Because the first-layer signal wiring for interconnecting the basic cells is formed in a separate wiring layer independent of the second-layer power supply voltage wiring and second-layer reference-voltage wiring, it can be extended in the direction crossing those wirings. The first-layer signal wiring cannot be extended in the second direction because the first layer power supply voltage wiring and first-layer reference-voltage wiring are arranged in the same wiring layer with the first-layer signal wiring formed. That is, basic cells can be interconnected only in the first direction and a macro-cell having a predetermined logical function can be configured by combining a plurality of basic cells in the first direction.
For intraconnections between the above basic cells, the first-layer signal wiring formed integrally with the first-layer signal wiring used for interconnection in basic cells is used. Therefore, an area where the second-layer signal wiring is formed and which is for connection with the second-layer signal wiring, so-called a wiring channel area is not interposed. That is, in the semiconductor integrated circuit device reported in the above-mentioned art, the wire length between basic cells can be decreased compared with the case that the wiring channel area is provided by omitting the wiring channel area between the basic cells in a macro-cell. Therefore, the signal transmission speed can be increased and the operation of the macro-cell can be accelerated. Moreover, the area occupied by the macro-cell can be decreased and the integration degree can be improved by the decrease in area of the omitted wiring channels between the basic cells.
However, the semiconductor integrated circuit devices to which the above-mentioned art is applied is not considered in view of the following points.
(A) Because the first-layer signal wiring of the above macro-cell is limited in its extending direction and can be extended only in the first direction, basic cells can be interconnected only in the first direction. When designing a macro-cell, a circuit is assigned successively to each basic cell arranged in the first direction. If some unconnected and unused MOSFETs are present in a basic cell, they can be used when basic cells having unused MOSFETs are adjacent to each other or arranged relatively closely to each other.
However, the first-layer signal wiring cannot be extended in the second direction because the first-layer power supply voltage wiring and first-layer reference-voltage wiring are arranged. That is, when unused MOSFETs are present in a basic cell, they are completely useless elements even if unused MOSFETs are not present in adjacent basic cells or those arranged relatively closely to each other and some unused MOSFETs are present in basic cells arranged in the second direction. Therefore, the integration degree of the semiconductor integrated circuit device lowers because the probability that unused MOSFETs are present in a macro-cell increases (the effective availability of elements decreases) and the area occupied by the macro-cell increases.
(B) If many unused MOSFETs are present in a macro-cell, the wiring lengths in basic cells and these between basic cells increase by the extra length necessary when the wiring is laid passing through or away from the unused MOSFETS. Therefore, the signal transmission speed in the macro-cell and the circuit operation speed of the macro-cell decrease.
(C) As the integration degree and operation speed of circuits are improved, the number of MOSFETs arranged in the unit area increases and the power consumption also increases proportionally to the increase of the number of MOSFETS. Therefore, it is required to enhance the power supply capacity. Enhancement of the power supply capacity can simply be settled by increasing the width of each power supply wirings of the first-layer power supply wiring, first-layer reference-voltage wiring, second-layer power supply wiring, and second-layer reference-voltage wiring (that is, by decreasing the current density).
However, because the increase of the power wiring widths decreases the number of MOSFETs arranged in basic cells, the integration degree of the semiconductor integrated circuit device lowers. Also, because the increase of the power wiring width decreases the number of wirings in basic cell and that of wirings between basic cells (number of first-layer signal wires) and increases the number of unused MOSFETs which cannot be interconnected due to lack of the number of wirings (that is, lowers the effective availability of elements), the integration degree of the semiconductor integrated circuit device lowers. Moreover, when the number of wirings in a basic CEll and that of wirings between basic cells are small, it is necessary to provide a wiring channel area in another area. Therefore, the integration degree of the semiconductor integrated circuit device lowers by a degree corresponding to the increase in the area occupied by the wiring channel area.
(D) As the integration degree and circuit operation speed are improved, the number of signal wirings arranged in a unit area increases. Therefore, many crosstalk noises (coupling noises) occur between adjacent signal lines, decreasing the reliability of circuit operation of the semiconductor integrated circuit device.